Integrated circuits are connectable to “the outside world” through input nodes, output nodes, or input/output nodes such as bond pads, input pads, input/output pins, die terminals, die pads, or contact pads. Buffer circuitry, often configured as an inverter, is interposed between such nodes and active circuitry of the integrated circuit. The buffer circuitry typically includes transistors which should be protected from over-limit electrical conditions, for example, voltages caused by electrostatic discharge (ESD) during handling, testing and operation of the integrated circuit. Subjecting a device to ESD is referred to as an ESD event. An ESD event is an example of an over-limit electrical condition that may cause damage to the circuitry of the integrated circuit unless adequately protected. Typically, an ESD protection circuit, which is well known in the art, is connected to a node, such as a bond pad. One example of an ESD protection circuit includes diodes connecting a bond pad to power rails. The ESD protection circuit protects the transistors from high voltages caused by an ESD event. The ESD protection circuit keeps the potential of the bond pad from exceeding a maximum value.
Although the ESD protection circuit is designed to withstand high current levels, the bond pad potential may be greater than the breakdown voltage of the buffer transistor. This may be especially true for buffer transistors fabricated using current CMOS technologies, in which case the thickness of the gate insulator of the buffer transistor has decreased from the thickness obtained using previous fabrication technologies. As the thickness of the gate insulator decreases, the breakdown voltage of the gate insulator decreases. Consequently, the breakdown voltage of the buffer transistor is often below the potential established on the bond pad by the ESD protection circuit.
As semiconductor technologies have evolved, the standard voltage for representing a logical high signal has been being reduced from an earlier standard of 5 volts to an increasingly common 3.3 volts. For reasons relating to, among other factors, power consumption, thermal performance, speed, and device size, it is entirely possible that the standard voltage for representation of a logical high signal could be reduced even further as semiconductor technologies evolve.
The shift to lower operating voltages in semiconductor devices has not occurred all at once within the semiconductor industry. There has been an ongoing desire for semiconductor devices which are capable of recognizing a range of logical voltages, for example, recognizing either 1.8 volts or 2.5 volts as a logical high signal. Even for semiconductor devices intended to operate only at one operating voltage, however, care must be taken to ensure that the device can withstand an occasional or even sustained overdrive condition without adverse consequences. Those ordinarily skilled in the art will understand that the term “overdrive condition” is used to refer to voltages or currents at an electrical node, such as at an input pad, which exceed specified levels, such as a manufacturer's specification of the “normal” operating parameters for the device. Overdrive conditions can be contrasted with what is typically referred to as a normal operating conditions, that is, conditions specified by a semiconductor device manufacturer to be within specified limits. By way of example, for an input/output pin on a semiconductor device specified for operation with a supply voltage of 3.3 volts, a voltage of greater than five volts present on that pad might be considered an overdrive condition. As known, overdrive conditions may cause over-limit electrical conditions that may damage circuitry.
Typical over-limit electrical condition protection circuits include circuitry that provide a low-impedance conductive path to a reference voltage, such as ground, to dissipate the over-limit electrical condition before operational circuitry of the integrated circuit is damaged. Many of the protection circuits include circuits that exhibit a “snap-back” characteristic. Generally, a snap-back characteristic provides a trigger condition which when exceeded, causes the circuit to enter a low-impedance state. The low-impedance state is maintained while the electrical condition on a node exceeds a hold condition. Examples of conventional circuits having snapback characteristics include thyristors, such as silicon controlled rectifiers (SCRs), and overdriven metal-oxide-semiconductor (MOS) transistors, and diodes.
In designing an adequate protection circuit using a snapback circuit, the trigger condition must be sufficiently low to provide protection before a breakdown condition occurs for operational circuitry. Examples of conventional circuits having set trigger condition, and typically the hold condition as well, include diode-triggered SCRs (DTSCRs). Once set, however, adjusting (e.g. changing, altering, etc.) the trigger condition, however, often requires redesign of the protection circuit. That is, the protection circuits are typically “hard-wired” and are not modified after the integrated circuit is fabricated. Moreover, trigger conditions for ESD protection and protection against latch-up conditions are often different, thus, having a protection circuit having a trigger condition set to protect against one condition may be a compromise for protecting against the other over-limit electrical conditions.